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ADV7401
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing refer-
ence signals are provided. In DDR mode, the ADV7401 can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.
The ADV7401 is capable of supporting an external DVI/
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7401 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the
I 2 C interface. For more detailed product information about the
ADV7401, contact your local ADI sales office or email
video.products@analog.com.
HDMI receiver. The digital interface expects 24-bit 4:4:4 or
16-bit 4:2:2 bit data (either graphics RGB or component video
YCrCb), accompanied by HS, VS, DE, and a fully synchronous
clock signal. The data is processed in the CP and output as
16-bit 4:2:2 YCrCb data.
Rev. B | Page 16 of 20
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